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How to move specific file from one directory to another one
Hello Everyone,I have netlist abc.cdl in my PWD ,ALSOMy setting file is in other directory...also setting file path differsi want to move my abc.cdl file from PWD to above test/info directory.How to...
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Write a text file to cell
How do I write a text file to a cellI want a I can use this for layout/schematic/symbol ( dbOpenCellViewByType )Is there a option to create a text file or is there another way?Paul
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Re: prevent string choices of verilogA from splitting into two lines
Hi,I created a verilogA block to generate different static output depending on a parameter call Mode that can have two values, "power down" and "calibration". This verilogA is instantiated on a...
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Failed to get the manufacturing grid after stream in
Hello,When I open a cellview in the library after import a GDS file, CIW showed a warning:*WARNING* (GE-2125): Failed to get the manufacturing grid (mfgGridResolution) for the technology tech.db...
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"Verilog in" setup question and compile *E NOTDIR when use config to open...
Hi Supporter,When I use AMS try to do mixed-signal sim , that have some errors like below:Firsr I doubt the error is occured at "verlog in" step, But the log is OK, and "verilog in" finished that not...
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Transient plot of broken asserts
Hi all.I am using IC6.1.8-64b.500.10.I have table with asserts which is generated using asserts .scs file:Navigating to to schematic for a device that is causing break of assert works by clicking on a...
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Saving more parameters of MOSFET during transient simulation
Hi all.I am using IC6.1.8-64b.500.10.For DC sweeps I can enlarge list of saved parameters for specific MOSFET by creating .scs file and adding it to definition files.Content of mentioned .scs file may...
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How to export/write-out a layout/schematic/symbol view as SKILL?
Hi,In the past, I've used a build-in procedure to write-out (or export) a view as SKILL file. You could see this output file as a sort-of replay file. I'd like to do the same again, but I don't...
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Sonarqube plugin for SKILL code
We are looking for static code analysis of our SKILL code. Is there any plugin available to do so via Sonarqube? Or is there any native solution already available. Please help!
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How to confirm connections which are connected by "net name" in visible way
Hi Sir,Some circuits in schematic are connected by only net name, I need to check the connections are correct or not.I hope a prepared script by cadence but there is not good tool (or I couldn't find...
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How to create and add submenu options in virtuoso window
Hello ,am using below code to add Cadence option menu in virtuososetupItem = (hiCreateMenuItem ?name 'Setup ?itemText "Setup" ?callback "(println \"WELCOME TO CADENCE\") Switches()" )Menu =...
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How to move custom_menu items to pre-existing menu items
Hi there,I have created a custom menu i.e Main Menu..by below following script-procedure(Menu_CIW_TOP()ciwMenuInit()menuItem_11=hiCreateMenuItem(?name 'item11 ?itemText "ITEM 11" ?callback...
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pcell streamout with different cell name
I have a layout view that contain a "crtmom" and a "crtmom_mx" in IC617. "crtmom" and crtmom_mx" are both pcell, but pcell "crtmom_mx" contain pcell "crtmom", refer the following fig.when i streamout...
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Just some pcell info
I have done some small pcells in layout, but is the difference or defines a pcell for schematics??What are some of the things to be aware of when doing schematics pcells??Paul
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Changing schematic properties and callbacks
Hi,I am in the process of evaluating a new PDK and I would like to run some sweeps for different geometries and device types.The issue with sweeping "the standard way" is that this substitution process...
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Assura DRC for Dummy Fill Generation
I'm trying to generate auto-fill patterns using Assura DRC.Below is the sequence that I'm thing about:1. scan the whole chip and divide up into pieces. 1) find the rectangluar spaces that can fit...
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Layout of Memristor
Hello All,I have done simulation for my project with spice code of Memristor in cadence virtuoso and now I want to do layout for the same. But, as it is not defined for the layout of memristor. Could...
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How to export GDS file of PCell instance (submaster)
I am trying to write a Skill script to walk through a schematic and generate a GDS file for each PCell submaster in the schematic. I am new to Cadence, so I may misuse some terminology.My first attempt...
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How to reduce the runtime of gc function called by system?
Currently I write a SKILL code and find out the run time of gc function takes more than the main function I use in SKILL IDE information(~10x).This is a system call function to do garbage...
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Can I remove session from preSaveOceanScript Skill function?
I've code that registers a custom skill function withenvSetVal("asimenv.misc" "preSaveOceanScript" 'string "MyFunc")MyFunc is defined to have session and fp as arguments. However, session is unused....
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