I am trying to create a behavioral view and I get this error/warning.
How can I suppress it?
Regards
Genas
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How can I suppress this warning
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Toggle a grid switch
Should be easy, but can't figure out where it is wrong.
Lint score is 100.
Tried "nil" with and without quotes.
Purpose = Toggle the fb1 grid on or off with a bindkey.
Flow:
1. get grid visible status.
2. if on then turn off.
3. if off then turn on.
Problem: Turns it off but won't toggle it on.
code starts here:
procedure(MDTtoggleFB1( )
if( pteIsVisible("Grids;Snap Patterns;Local Grids;fb1" "Grids") == "nil"
then
pteSetVisible("Grids;Snap Patterns;Local Grids;fb1" t "Grids")
else
pteSetVisible("Grids;Snap Patterns;Local Grids;fb1" nil "Grids")
)
)
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Increasing metal width of entire net in cadence layout
Hi Team,
I had got net plot using cvPplot(). Now i want to increase the metal width of entire net by delta X which consists of different metals.
Is there any option to increase the metal width through SKILL code?
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Schematic net highlighting control
In the schematic display options form there are 3 controls for fine tuning net highlighting - Dynamic Highlighting (on/off), Dynamic Net Highlighting (on/off) and Connect by Name Highlighting (on/off). I like the first two to be on but the last one to be off because it's just too visually jarring and disruptive while moving my mouse around. In my .cdsinit I can control the first two using the following commands:
envSetVal("schematic" "symDynamicHilightOn" 'boolean t)
envSetVal("schematic" "schDynamicNetHilightOn" 'boolean t)
however I'm darned if I can find any way to define the last one. Any ideas?
I also saw an earlier post that referenced an envSetVal command that tweaked schDynamicNetHilightNoIslands - I couldn't see that in the documentation. What does that do? Thanks.
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inverse statistics error function in SKILL
Hello all.
Python has an inverse error https://stackoverflow.com/questions/31266249/command-for-inverse-erf-function-in-python
Other languages have it too, I have tried to find this in SKILL Core and VIVA, and could not.
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Unable to use instance option
Hi,
I have recently updated my PDK and I noticed that there are some issues with using "I" or Create-> Instance to add instances. When I restart the cadence everytime by sourcing the cad file, I could place instances the first time. Then when I use the command again, I get an error in the log window. I could not understand this error or which file it refers to.
When I start the cadence, there are warnings indicating the problem with the instance option. Can I get some help on how to fix this?
Thanks,
-Rakesh.
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Ocean - variable as an input argument of 'axlAddOutputs'
Hi All,
When i try running the two following lines (in my Ocean script):
current_names = list("iref", "vref")
axlAddOutputs(current_names)
i'd get the following error:
*Error* car: argument #1 should be a list (type template = "l") - current_names
Whereas the following line would run with no errors whatsoever:
axlAddOutputs(list("iref", "vref"))
I would like to create the list separately (and only once) in order to use it in different parts of my script.
Does anyone have an idea on how to make those first two lines run? Or maybe another way to approach this that i haven't come up with?
Thanks,
Asaf
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grep doesn't work from system(), but does from terminal, how to fix?
Hello,
As part of a script to fix port-orders (yes, I know, we could have a whole debate about port-order or terminal order, but let's park that for now...) I want to automatically process a CDL netlist file using a combination of grep and sed, in order to create a new file which will be used by the SKILL script. This is the tried and tested command which does exactly what I want, and it runs perfectly from a terminal:
grep -Pzo '.SUBCKT P.+\n.*' /users/sh033860/workarea/xp4000/scripts/io_gppr_cln22ul_t25_mv09_mv33_fs33_svt_dr.cdl | grep -v '^*' | sed 's#.SUBCKT ##' | sed -z 's#\n+##g' | sed 's# #,#' > termOrder.input
It reads a CDL netlist file, looks for all lines that start with ".SUBCKT P", selects this whole line AND the next line. The second grep removes all lines which start with a "*". Multiple sed commands are used to remove the ".SUBCKT P" part, replace a new-line and + with nothing and finally it replaces all spaces by a ",". This all is stored in the file termOrder.input.
This all works from the same terminal from which I launch Virtuoso.
Since I want to automate this into the script, I tried the following in the CIW:
sourceNetlist = "/users/sh033860/workarea/xp4000/scripts/io_gppr_cln22ul_t25_mv09_mv33_fs33_svt_dr.cdl"
command = strcat("grep -Pzo '.SUBCKT P.+\n.*' " sourceNetlist " | grep -v '^*' | sed 's#.SUBCKT ##' | sed -z 's#\n+##g' | sed 's# #,#' > termOrder.input" )
system( command )
And this fails... The output in the terminal is:
[tsmcN22@utc0vnc002 cds]$ grep: the -P option only supports a single pattern
sed: -e expression #1, char 2: unterminated `s' command
However, when I first open a terminal from the CIW by doing this:
system( "xterm" )
And then, in this new terminal past the same line as constructed by command = ....., it works.
I truly hope someone can explain to my why it doesn't work from using system( command ), but it works manually. It would be very handy to be able to automate this step (and I will use this more often in the future).
Having said that, if something like this can be done fairly easily using SKILL (reading a CDL file and processing it on the fly), I'm more than happy to do it like that.
Many thanks in advance.
With kind regards,
Sjoerd
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exporting layout into a file (SKILL)
Hello. I am using virtuoso version ICADV12.3-64b and I need to export the layout of my design into a file so that I can modify the layout using SKILL and then use it for simulation?
I am a beginner in this and all I know is that the current version of virtuoso does not export the layout into the CIF file. what are my options? which file format can I export from layout? how do I export that?
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DSPF with veriloga
Hi,
I have a query related to the use of DSPF of a design with veriloga model of a subblock in the same design. I am working on a macro which has a huge counter, so to speed up the simulations we use a Veriloga model of the counter and run schematic based simulations. Now, if I am giving dspf as an input with the veriloga model for the counter block and the dspf is mapped to the schematic, then will the tool take the dspf for the rest of the blocks in the design and veriloga for the counter block. Is my understanding correct?
Que 2) Is there a faster way to simulate the dspf without veriloga ? I have tried using APS++ and keeping liberal settings with post layout optimizations turned-on but as the counter is operating at 1GHz frequency and will count upto 4ms of time. Hence, its taking huge time in simulating the design. I have also tried using hspice simulations which gives me results in 3-4 days. But Is there an option in adexl where i can reduce the run time in polo simulations using virtuoso?
Thanks and Regards,
Aniket
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Highlight selected net in Layout XL (and schematic)
Hi,
Some details on my request/question as below;
Virtuoso: ICADV12.3-64b.500.23
Task: Layout creation from schematic using Layout XL
Problem:
I am looking for a better/more efficient way to highlight nets while doing routing and LVS fixing.
While I have used net Marking (Connectivity -> Nets -> Mark), the marking does not update once I added/removed a wire to the net, unless Unmarking and Marking again.
Same goes for the Net Tracer (Connectivity -> Net Tracer @ Window -> Toolbar -> Net Tracer), which does not update the trace upon adding/removing wire to the net.
Both (Mark and Net Tracer) also does not highlight the corresponding net in Schematic, and does not show flightlines for open/incomplete net.
Using the Annotation Browser (Window -> Assistant -> Annotation Browser) is somewhat useful, though there are cases where the flightlines are not actually where the nets are.
I then need to use Net Tracer to see clearly the exact wire routing.
Currently I am using XL Probe (Connectivity -> XL Probe). It is good that it is probing the net in both Layout and Schematic. Plus that the probe updates every time I adds/removes wire to the net, and flightlines are there for open/incomplete net.
However, with hundreds of nets to look at, with the non-expandable XL Probe window, scrolling through the list becomes quite repetitive.
I am fully aware of the Net Name Filtering Option (though I have not used it yet).
I would like to have a similar probing functions as XL Probe.
However, instead of selecting the net(s) to be probed from the XL Probe window, I want to select the net(s) first, and then pressing a newly assigned bindkey (I will take care of that part) to probe the net.
Alternatively, if the XL Probe window can be turned into something like the Annotation Browser (attached to the Layout XL, instead of opening and closing it every time I want to probe), that would be good as well.
Side question, can the probe highlight color be increased from 10? Is it customizable?
Appreciate any help I can get.
Thanks,
Shin
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"minEnclosure" constraint for layer "M1" and layer "CA" is deprecated problem when setting up minimum enclosure distance in the layout's technology file.
Hi All,
I want to set the minimum enclosure distance between layer "M1" and "CA" in the layout using the SKILL ommand,
techSetOrderedSpacingRule(tfId "minEnclosure" 0.7 "M1" "CA"),
but I got Warning message in CIW like these,
*WARNING* (TECH-230024): techSetLayerPairConstraint:
"minEnclosure" constraint for layer "M1" and layer "CA"
is deprecated. You should use "minOppExtension" with the same
value for two extensions. For backward compatibility,
the constraint will continue to be stored in the database and will be
accessible with APIs. When the technology database is dumped to ASCII,
it will be dumped with the correct mapping("minExtensionDistance").
t
I'm using IC618, please help.
Best regards,
Marben
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How to remove a file
Hello,
I want to remove a file (from the filesystem). How can this be done with SKILL? I've checked the API finder, but could not find anything suitable.
Kind regards,
Patrick
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Cannot add delta marker between horizontal cursor just as vertical does
Hi all,
As titled, I have no idea about how can't I add the delta maker between the horizontal cursor.
Please tell me how can I fix it if you know. Thanks a lot.
Here is the screenshot of the ADEXL result browser.
And this is what the CIW shows.
Sincerely
Thanks
Daniel
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Rotate form automatically popup when press Bindkey of schHiRotate(t)
schHiRotate(t) has a option form of " rotate form" (sideway/right/left/..), how can I make it automatically popup after i press <Key>R ?
I know "options displyed when commands start" in CIW->option->userpreference, but this will also enbale all other option forms. I know <Key>F3 to hiToggleEnterForm(), But this is also not what I want.
I tryed "changEnterFunction() ?alwaysMap t" but failed, because i dont know how to map "schHiRotate(t)" and its "option Form" in correct way/format, dose anyone know the solution? thanks!
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Effective R calculation showing NA
Hi,
We are using IC6.1.8-64b.500.11
which spectre:
/tools/pdk/F01/U130S4/7.2/tools/mmsim18.10.463/tools/bin/spectre
spectre -W:
sub-version 18.1.0.463.isr10
I have been trying to backannotate "my_cell" with effective R value. "my_cell" is schematic with series of 3 resistors and two pins "in" and "out". I made a config view TB using av_extracted_RC(using PVS-Quantus) view of "my_cell" and ran a dc simulation with DC input of 1.2V at "in" pin. I have kept "Save DC Operating Point" enabled and saving all voltage and current nodes from the Output options in ADEL. After simulation ended I descend into schematic view of "my_cell"(out of context). Then I go to Parasitics->Setup which already had result directory correctly filled under "Results directory for R calculation". When I go for "show parasitics" option, it gives me capacitance values of each net but R is shown as "NA". Can you help me with where am I going wrong?
List of images/files
1. my_cell schematic
2. Output->save All form of ADEL
3. setup Parasitic form
4. Netlist
community.cadence.com/.../input_5F00_scs.txt
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Is there a way to give a procedure access to it's argument list as a string?
Say I have something like:
var1=vector(1 2 "abc" 3 4)
var2=vector("x" "y" "z")
and I define a procedure like:
procedure( myProc(arg1 arg2])
...blah...)
and I call the procedure with
myVar = myProc(var1 var2[1])
Is there any way to give the procedure access to the actual text of the arguments it was called with i.e. for the above example I'd like the procedure to be able to pick apart the string "arg1 arg2[1]". The reason I want to be able to do this is that I'd like the procedure to be able to peek into other elements of var2 even though it was only passed a specific element of it. Thanks!
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help with branch decision on layout heirarchy and DbConcatTransform
Hi Cadence -
need help with layout heirarchy. I have a layout cell where I have bunch of labels, and I am using dbGetOverlaps() for locating the underneath rectangle.
I'm using cadence 18.
My current flow is something like:
labelgroup=selectedSet()
foreach(label labelgroup
overlapShape=dbGetOverlaps(cvID label~>bBox layerUnderneath 3) ; look 3 levels down
) ; foreach
step1=dbConcatTransform(car(list) car(cadr(list))
step2 =dbConcatTransform(step1 car(cadr(cadr(list))))
shapePoints=dbTransformBBox(shape~>bBox step2)
the problem is "SOMETIMES" the shape I want isn't 3 levels down, it's actually 2 levels down.
The return list is *USUALLY* something like (db:xxxxxxx (db:xxxxx (dbxxxx dbxxxx))) the final pair is of course the rectangle and it's instance location
The problem is that I have *TWO* hardcoded concatTransform statements and then transformBBOX.
When the heirarchy level is 2 the second time I call concattransform I should be calling dbTransformBBox() and so the loop crashes.
I can't figure out , I need some sort of test for the structure (dbxxxx dbxxxx) , perhaps can I put concat transform in a while loop to check the list
length to find out if that rectangle db id is still down only one level. Thanks in advance. Malcolm
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how to read/modify the time/value pairs of vpwl/ipwl sources from analogLib in skill
Hi there,
I have some schematic test benches and I want to modify the time/value for some vpwl/ivpl sources using skill.
What is the best approach to do that?
From what I see I can read the vpwlId->tvpairs property and after that I can modify the (t1, v2), (t2, v2)...(tN, vN) properties of teh respective object.
Is it the right way to do it, or we have an API.
Thank you,
Marcel
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Is there a command to return the index of an element if it exists in a list or array?
Hopefully a quickie (and I did search the documentation beforehand). I'm looking for a command that will take an array (preferred) or list and an object return the index of the object if it exists in the array or list. I know I can use e.g. the member function and do a subtraction between the lengths of the original and member lists, but I was hoping there was a native command that just did what I was after. Ideally the command would look like:
myList = list(1 2 "ab" "ef" 1.234)
some_function("ef" myList) would return 3 (i.e. nth(3 myList) yields "ef")
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