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using local variables or "parameterized parameter" in graphical PCell

September 18, 2018, 4:23 am
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Hello,
I'm trying to edit an existing graphical PCell (layout) using IC6.1.6.
There are multiple stretches & parameterized properties that share a major part of their expression.
for example:
Stretch 1:
((evalstring(w)+2.0+dx)*(nx-1))
Inherited Parameter 1:
(xTotal-((evalstring(w)+2.0+dx)*(nx-1))+0.02)

I thought about using parameterized property for the shared part, however they would not accessible within the layout.
Another idea was to use letseq with the intention to make it easier to make changes, however this would still require to change all expressions.
Besides that, there seems to be a small bug, as the parameter "width" is automatically added to the pcell parameters, even if this parameter is not used.
Stretch 1:
letseq(((w evalstring(w))(width (w+2.0+dx)*(nx-1)))) width)
Inherited Parameter 1:
letseq(((w evalstring(w))(width (w+2.0+dx)*(nx-1)))) (xTotal - width + 0.02))
Is there any flexible way to implement that?
thx in advance & best regards,
Michael
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Move or copy across layout hierarchy

September 18, 2018, 9:15 am
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Hi,

Is there any skill procedure available to copy/move layout objects from one hierarchy to another?. The usage will be like this,

1. EIP to a level

2. Select the objects to be moved or copied (Ctrl+X or Ctrl+C)

3. Come out one/multiple level above.

4. Paste the objects in same location as how it was inside the hierarchy (Ctrl+V)

Similarly from top level to lower levels

-Ramakrishnan

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Using an OCEAN script to select different simulation views

September 19, 2018, 3:53 pm
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I come from a background where pretty much all aspects of a simulation were controlled via scripts and not GUIs. Is there a way in OCEAN to define and manipulate the simulation views e.g. as the hierarchy is traversed use a Verilog-A model if found otherwise keep traversing until you find a primitive device model? You would also be able to accumulate a few such commands to define a default precedence followed by other commands targeting different hierarchical levels to explicitly define different precedences for those levels. For example, let the digital & timing blocks (and all of their hierarchy) be modeled in Verilog-A, let this analog block use a structural schematic view (made up of VCVS's etc.), and let the remaining analog signal chain blocks and all of their hierarchy be modeled as transistors (even though they may have existing Verilog-A models). You could quickly define and implement large scale changes to the simulation environment with just a couple commands. I find when I use GUIs that things can become obfuscated - in a script I can add comments and stuff to self-document the process and that kind of gets lost in the GUI world.

I hope the above made sense...

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skill code to place all symbol cells in a virtuoso lib to top level schematic cell

September 20, 2018, 7:06 pm
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Hi All,

I was trying to create a top level schematic which has all the symbol of cells in a schematic. What I have is 

##########create a test schematic with inv symbol in it ###############

cv=dbOpenCellViewByType("sc33tps_v1" "test" "schematic" nil "a")

 cv1=dbOpenCellViewByType("sc33tps_v1" "inv"  "symbol")  
  schinst=dbCreateInst(cv cv1 nil list(0 0) "R0" 1)    

this code is working fine

#############################################################

now I want to place all the cell in "sc33tps_v1" lib in test schematic and I have 

cv=dbOpenCellViewByType("sc33tps_v1" "test" "schematic" nil "a")  
lib=ddGetObj("sc33tps_v1")
foreach (cell lib~>cells
  when(ddGetObj(lib~>name cell~>name "symbol")
      cv1=dbOpenCellViewByType(lib~>name cell~>name "symbol")   
      schinst=dbCreateInst(cv cv1 nil list(0 0) "R0" 1)    
)
)
 

this code is not working . Please help to let me know what is wrong ? 

thanks 

Nhumai 

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Saving node voltages in Cadence

September 21, 2018, 2:12 pm
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I am trying to save 'all' the net voltages inside 'some' of the blocks in my circuits. I would like to emphasize that I am not intending to save all the net voltages inside the 'entire' circuit. In order to save all the nets inside a specific block and the top level, I use statements as follows:

save * depth=1

save mmdiv.* depth=2

save mmdiv.REG.* depth=3

saveOptions options save=selected currents=selected

However, I noticed that net names starting with '0' such as net012 or net0221 do not get saved where as others such as net45 or net32 do get saved. Would you please guide me as how I can resolve this issue?

Thank you,

Alireza Razzaghi

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need a gui based remaster script for cells

September 24, 2018, 8:14 pm
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I wanted to replace the cells in the schematic from one lib to other and potentially different cellname

I wrote the following SKILL code:

;; liblist=ddGetLibList()~>name
;; cellist=ddGetObj("smaurya_l")

procedure( replace()
let((oldcellnameL oldcellnameS)
liblist=ddGetLibList()~>name

libNameOld=hiCreateListBoxField(
?name 'libNameOld
?numRows 6
?choices liblist
?prompt "Old Library Name"
?callback "oldcellnameL=(libNameOld~>value) println(oldcellnameL) sprintf(oldcellnameS \"%L\" oldcellnameL) println(oldcellnameS)"
)
println(oldcellnameS)
cellNameOld=hiCreateListBoxField(
?name 'cellNameOld
?numRows 6
?choices ddGetObj(oldcellnameS)~>cells~>name
?prompt "Old Cell Name"
?callback "ddsUpdateSyncWithForm()"
)
;;new
libNameNew=hiCreateListBoxField(
?name 'libNameNew
?numRows 6
?choices liblist
?prompt "new Library Name"
?callback "ddsUpdateSyncWithForm()"
)
newcellname=ddGetObj('libNameNew)~>name
cellNameNew=hiCreateListBoxField(
?name 'cellNameNew
?numRows 6
?choices newcellname
?prompt "new Cell Name"
?callback "ddsUpdateSyncWithForm()"
)

randFrameField = hiCreateFrameField(?name 'myrandFrameField)
netlisterForm = hiCreateAppForm(
?name 'netlisterForm
?formTitle "Replace"
?fields list(
list(randFrameField 5:0 405:100)
list(libNameOld 10:10 400:100 100)
list(cellNameOld 10:100 400:100 100)
list(libNameNew 10:190 400:100 100)
list(cellNameNew 10:280 400:100 100)

);fields
?buttonLayout 'Close
?initialSize t
) ;hiCreateAppForm

hiDisplayForm(netlisterForm)
);let
);procedure

;;procedure( celllist(libname)

I wanted the user choose the library and then select the cells from that list.I am able to get the library list but somehow I am not able to populate the celllist of that library. I am using callback to pass on selected libname to the celllist but its always empty.

Is there a way to set variable in callback section and use it later.

Satendra'

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Finfet Pcell creation

September 26, 2018, 9:32 am
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Hi,

Need guidance in developing pcells for finfet.

Kindly help.

Regards,

Praveen

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Displaying special characters in the Units column in the Assembler 'Outputs Setup'

September 26, 2018, 3:04 pm
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In my assembler testbench I am trying to display units that are not regular ascii characters.

In one particular case it would be nice to display 'pA per root Hertz' as pA/???Hz,  where ??? is the square root symbol

In the 'Outputs Setup' tab I would put the 'p' in the Suffix column and the rest in the Units column.

Although printf("A/\342\210\232") will correctly display in the CIW, entering A/\342\210\232 directly  in  the Units column or by loading it by a CSV file does not work.

It is displayed literally.

As I am reading these units from some specifications it would be awkward to have to deal with the non-ascii code  (I already have modified the unicode to be in octal byte format).

It there a way to get these octal bytes interpreted?

Thanks

Paul

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Skill code to list "all the transistor hierarchical path along with their size (e.g fin number, number of finger, length) on given net"

September 26, 2018, 4:08 pm
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Need Thumbnail warnings explanation

September 28, 2018, 12:57 pm
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Hi,

I have a skill function that processes layout view in all cells of given OA library. At the end of operation I got multiple warnings like below, as many as the number of cells in my library:

*WARNING* Thumbnail window was requested, but has already been closed

I'd like to fix them as this skill code will be used by other designers but cannot find what is the reason and what I do wrong. What I've tried so far was to manually create thumbnail with hiGenerateThumbnails() function and double check that every view and library object are properly saved, closed and released: dbSave(cv), dbClose(cv), ddReleaseObj(cellId).

Any hint or explanation of this warning root cause will be greatly appreciated.

Thank you,

Misha

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missing libraries

September 28, 2018, 1:18 pm
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Hi,

I'd like to hunt down libraries that are referenced on layout but not included in my cds.lib file so now I'm looking for flashing boxes with my own eyes.

Is there any easy way to find them at a time?

Thanks,

Jungyoon

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Simple question about repeated list elements.

September 28, 2018, 3:25 pm
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In my simulation scripts I'm doing a lot of waveform plotting using the awvPlotWaveform() function. Say I'm simulating over PVTs and want to plot a lot of waveforms in a separate color per PVT.  I have the color stored in a variable (color_var) so the relevant part of the plot command contains the text:

?color list( color_var color_var color_var color_var color_var color_var color_var color_var color_var color_var color_var color_var ) \

and I have the same thing for the plot_strip etc.. 

I searched and I searched but I couldn't find any way to define a list of repeated elements easily e.g. something like

list( 20*color_var) 

I know the above syntax can't possibly work, but is there anything that does what I want?

(Note: I originally posted this about the strip_number in the awvPlotWaveform function but the forum's automated spam detector rejected my post as offensive because it contained the word strip too many times :-/)

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How to change the simulator via skill in ADE-L?

October 1, 2018, 2:39 am
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Hi All

I am currently writing a script to export the necessary input files for the amsd block in the AMS simulation.

On the other hand, I need some pre-configuration through the config file to get the right schematic view in the final netlist.

When config is used for ADE-L, it has tendency to use "ams" as the simulator. Then the netlist is in the verilog-ams syntax.

In order to have netlist in spectre syntax, I need to change the simulator to "spectre".  And I want this is automatically done.

While going through the skill reference for ADE-L, it seems the simulator is referred as "tool". And ADE-L session is created from the tool.

And unfortunately, I did not find an API to switch the tool for a session.

Does anyone have a clue for changing the simulator with skill?

Many thanks in advance.

Best Regards

Yi

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How to read current flow into a schematic symbol terminal using SKILL?

October 1, 2018, 5:19 am
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Hello SKILL experts,

I am fairly new to SKILL and have a basic doubt. I have searched for a solution in the Community Technical Forums for hours but was unable to get any help. The problem is as follows,

I want to conduct a DC operating point analysis for my schematic (which I did using an OCEAN script and selected dcOp results) then I want to read the current input into a symbol's (generated from a schematic) terminal. I want to automate the above task so I use the i("/symbolname/terminal") to access the current. The thing is that the valid outputs (returned by the outputs procedure) contains hierarchical addressing schemes, for example: My symbol is called "I27" and has a terminal named "R" so I try to get the current using i("/I27/R") which does not work, according to outputs(), what I should be using is i("I27/R0/PLUS"). Is there a way to convert my terminal name to a hierarchical name? or is there some other workaround to do the above task?

Thank you

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compare pins from 2 symbol

October 1, 2018, 10:08 am
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How to compare pins from 2 different symbols in virtuoso using skill code ?

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PVS LVS error in Finfet Cadence GPDK

October 5, 2018, 8:36 am
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Hi,

I have recently started to play with Cadence Finfet GPDK. I design a simple inverter and run Spectre simulation on schematic and it is fine. However, the layout has several problems. The first thing is that I do not know how to generate bulks in this PDK. I knew that NCSU 15nm FinFET has a specific PCELL bulk for all P and N transistor. Unfortunately, the documents are limited and I did not find the answer from the PDK doc. 

Would you please let me know if there are more documents available for this PDK? If there is a layout design example I can access?

When I try PVS LVS, I will have the following errors:

 
Layout Pin: VDD | Schematic Pin: VDD
=====================+================(sao 1)
Layout Net: X1/5 | OPEN
=====================+=======================


Layout Pin: In | Schematic Pin: In
=====================+================(sao 2)
Layout Net: X1/1 | OPEN
=====================+=======================


Layout Pin: GND | Schematic Pin: GND
=====================+================(sao 3)
Layout Net: X0/2 | OPEN
=====================+=======================

Any idea about this problem? 

Thanks for your help

Mohammad 

 

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simulation with huge number of duplicated caps

October 5, 2018, 12:09 pm
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hello experts,

we have design with thousands of duplicated caps. the simulation speed is quite slow for so many devices working together. is there some switch for the simulator to know that these duplicated caps are between same nodes so actually they can be combined into single big cap to speed up the simulation?

e.g., between A and B nodes there're 1000 caps of 1fF. can the tool combine them into single 1pF cap when running simulation?

thanks,

David

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PVS QRC problem in Finfet Cadence GPDK

October 8, 2018, 6:19 am
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Hi,

I have recently started to play with Cadence Finfet GPDK. I design a simple inverter and run Spectre simulation on schematic and it is fine. However, the documents are limited and I did not find enough information from the PDK doc. 

Would you please let me know if there are more documents available for this PDK? If there is a layout design example I can access?

After a while I could be able to pass PVS LVS but when I try PVS QRC without any parasitic (NO RC) the generated netlist for extracted layout is different from the schematic. I have provided schematic and extracted layout (by QRC) netlists as below:

************** Schematic netlist **************

 subckt test_schematic GND In Out VDD

    NM1 (Out In GND GND) cds_ff_mpt_n1hvt l=18n nfin=2 nf=1 m=1 ngcon=1 \

        asej=6.528e-15 adej=6.528e-15 psej=2.32e-07 pdej=2.32e-07 lrsd=18n

    PM1 (Out In VDD VDD) cds_ff_mpt_p1hvt l=18n nfin=2 nf=1 m=1 ngcon=1 \

        asej=6.528e-15 adej=6.528e-15 psej=2.32e-07 pdej=2.32e-07 lrsd=18n

ends test_schematic

************** Extracted layout netlist **************

  subckt test_schematic_av_extracted GND In Out VDD

    PM1 (X1\|10 In VDD X1\|11) cds_ff_mpt_p1hvt l=1.8e-08 nfin=2 nf=1 m=1 \

        ngcon=1 asej=1.904e-15 adej=1.904e-15 psej=3e-07 pdej=3e-07 \

        lrsd=18n

    NM1 (Out In\@1 X0\|9 GND) cds_ff_mpt_n1hvt l=1.8e-08 nfin=2 nf=1 m=1 \

        ngcon=1 asej=1.904e-15 adej=1.904e-15 psej=3e-07 pdej=3e-07 \

        lrsd=18n

ends test_schematic_av_extracted

It can be seen that transistors PM1 (or NM1) is connected to different terminals compared to schematic ones. For example, PM1 is connected to (Out In VDD VDD) in the schematic while in the extracted layout it is connected to (X1\|10 In VDD X1\|11).

Would you please let me know if you have any idea about this problem?

Thanks for your help

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create a pCell with m-factor

October 8, 2018, 5:48 pm
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hello experts,

I guess this could be very silly/easy question but puzzles me a couple days now. 

I have a customized cell and want to duplicate its instances. if I just make them as instance array (e.g., cell<1000:1>), it'll slow down my simulation dramatically. So I wonder if I can make it pCell with m-factor so that it'll be seen as single instance for the simulator. but I haven't done any pCell work yet. 

I came up following code from some examples I can find but still compliant there's something wrong. any idea or any better ways to achieve this would be greatly appreciated. 

pcDefinePCell(
list( ddGetObj("cell") "cell" "layout"
) ; end of list for first argument

(
( m "int" 1 )
) ; end of parameter list

prog(
let( lp )

; check parameters
m = if( (m<1) 1 m )

for( lp 0 count-1
  inst = dbCreateInst( d_cellView d_master nil 0:lp*1 "R0" 1 )

return(t)

) ; end of body-of-SKILL-code prog

) ; ; end of pcDefinePCell

thanks,

David

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change waveform line thickness with bindkey in ViVa

October 9, 2018, 9:25 am
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Hi, 

I am using IC 617.717 and I would like to know if exists a method to change waveform line thickness using/defining a new bindkey in ViVa.

e.g. I select a waveform, press bindkey "1" to set thickness to this waveform to "Fine",  and assign other thickness values to different keys ("2" Medium, "3" "Thick" "4" "ExtraThick")


I am aware I can do RMB->Width->"..." on a waveform but I would like to define a bindkey.

Please note that I am not referring to waveform viewer defaults set with envSetVal("viva.trace" "lineThickness" 'string "fine")

Best regards, 

Tommaso

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