I'm trying to write an Ocean script to simulate my circuit (comp_test) and within that script I want to fully define the "config" simulation state (e.g. schematic, spectre, verilogA...) of the various blocks within the schematic hierarchy.
I have a few lines of code that I've started out with:
1 hdbConfig = hdbOpen( "my_lib" "comp_test" "config_temp" "w")
2 hdbSetTopCellViewName( hdbConfig "my_lib" "comp_test" "schematic" )
3 hdbSetDefaultViewListString( hdbConfig "schematic spectre cmos_sch cmos.sch veriloga ahdl schematic0" )
4 hdbSetDefaultStopListString( hdbConfig "spectre" )
5 hdbSetObjBindRule(hdbConfig list(list( "std_lib" "rv" nil nil)) list('hdbcBindingRule list("std_lib" "rv" "veriloga")) )
6 hdbSave(hdbConfig)
7 hdbClose(hdbConfig)
8 design( "my_lib" "comp_test" "config_temp")
In line 5 I specify a given cell and force it to be executed as Verilog-A wherever it's encountered in the hierarchy i.e. this is a cell based command. I'm having trouble trying to figure out how I can specify a given cell (e.g. clk_gen, which contains a lot of hierarchy) and force everything within that cell to be executed as Verilog-A. I do not want to have to resort to making a line of code for every single instance contained within the full hierarchy of the clk_gen cell i.e. I'm effectively looking for a way to do wild-card configuration. Is this possible?