How to enforce schematic rule checker

Is there any way that I can ask the admin to put a piece of skill code in the library to enforce the following schematic rules?

1. Set all Verilog AMS Check rules to error in the Schematic Rules Checks Setup form and disallow users from changing it.

2. Force users to give a net or an instance an explicit name instead of the default net1234 or I1234 names.

3. Force users to use little endian bus notation B<msb:lsb> and lsb is always 0, i.e. B<5:0> is valid but not B<6:1> nor B<0:5>.

4. Force users to choose or avoid the pin/net/instance names from a customized pattern list.

I am using "@(#)$CDS: virtuoso version 6.1.6-64b 12/07/2015 20:18 (sjfbm186) $"

Thank you,

TJ